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Course topic

  1. Topics
  2. IT & Software
  3. Hardware Verification

Hardware Verification

Also indexed asHVL · Hardware Testing · FPGA Verification

Ensure robust and reliable hardware implementations through rigorous verification techniques.

Courses indexed
32
Live offers
9
Free & coupon courses onlyChange view
ASIC Verification using System Verilog (SV) + Project Demo
Instructor VLSI Mentor
VLSI Mentor
1 course
English
ASIC Verification using System Verilog (SV) + Project Demo

ASIC Verification using System Verilog (SV) + Project Demo

(4.50 with 79 reviews)
3.3K
students
19 hours
content
Jul 2025
updated
$17.99
Verification Series Part 6 : SystemVerilog Assertions Basics
Instructor Kumar Khandagle
Kumar Khandagle
1 course
English
Verification Series Part 6 : SystemVerilog Assertions Basics

Verification Series Part 6 : SystemVerilog Assertions Basics

(4.63 with 496 reviews)
3.7K
students
10 hours
content
Nov 2024
updated
$17.99
VLSI/FPGA Design P2: Verilog for Design and Verification
Instructor SKY SiliconThink
SKY SiliconThink
1 course
English
VLSI/FPGA Design P2: Verilog for Design and Verification

VLSI/FPGA Design P2: Verilog for Design and Verification

(4.60 with 5 reviews)
28
students
8.9 hours
content
Mar 2025
updated
$14.99
PCB Design: Designing Printed Circuit Board
Instructor Educational Engineering Team
Educational Engineering Team
1 course
English
PCB Design: Designing Printed Circuit Board

PCB Design: Designing Printed Circuit Board

(4.38 with 12 reviews)
1.8K
students
2.3 hours
content
Feb 2026
updated
$14.99
Formal Verification : Synopsys Formality Flow & Debug
Instructor Electronics Zone
Electronics Zone
1 course
English
Formal Verification : Synopsys Formality Flow & Debug

Formal Verification : Synopsys Formality Flow & Debug

(4.50 with 8 reviews)
213
students
1.7 hours
content
Mar 2026
updated
$14.99
RTL SDC Verification: Finding Timing Bugs Before Synthesis
Instructor Srinivasan Venkataramanan
Srinivasan Venkataramanan
1 course
English
RTL SDC Verification: Finding Timing Bugs Before Synthesis

RTL SDC Verification: Finding Timing Bugs Before Synthesis

(3.90 with 24 reviews)
448
students
1.1 hours
content
Nov 2025
updated
$14.99
Digital Design with SystemVerilog HDL + Introduction to UVM
Instructor Yoav Dror
Yoav Dror
1 course
English
Digital Design with SystemVerilog HDL + Introduction to UVM

Digital Design with SystemVerilog HDL + Introduction to UVM

(4.57 with 54 reviews)
200
students
2.3 hours
content
Dec 2025
updated
$14.99
AXI4 Implementations in FPGA Designs
Instructor Scott Dickson
Scott Dickson
1 course
English
AXI4 Implementations in FPGA Designs

AXI4 Implementations in FPGA Designs

(4.42 with 108 reviews)
1.1K
students
8.1 hours
content
Jan 2025
updated
$17.99
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Topics related to Hardware Verification

  • 01SystemVerilog17
  • 02UVM Verification12
  • 03FPGA Design52
  • 04RTL Design12
  • 05Verilog HDL36
  • 06VLSI Design46
  • 07ASIC Verification5
  • 08Testbench Development6
  • 09Assertions and Waits6
  • 10Digital Circuit Design60