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Udemy instructor

Kumar Khandagle

Teaches: IT & Software
Languages: English

Course index: 290 live offers
Students: 94.7K
Average rating: 4.41

First published: May 2020
Latest course: Apr 2025
Total content: 245 hours

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Instructor catalog

All Kumar Khandagle courses

Learning SystemVerilog Testbenches with Xilinx Vivado 2020

Kumar Khandagle

Learning SystemVerilog Testbenches with Xilinx Vivado 2020

Learning SystemVerilog Testbenches with Xilinx Vivado 2020

(4.55 with 93 reviews)

751

students

8.8 hours

content

Sep 2021

updated

$14.99

Resume Essentials for VLSI Internships and Entry-Level Jobs

Kumar Khandagle

Resume Essentials for VLSI Internships and Entry-Level Jobs

Resume Essentials for VLSI Internships and Entry-Level Jobs

(4.42 with 72 reviews)

2.5K

students

Verification Series Part 7:SystemVerilog Functional Coverage

Kumar Khandagle

Verification Series Part 7:SystemVerilog Functional Coverage

Verification Series Part 7:SystemVerilog Functional Coverage

(4.48 with 346 reviews)

3.2K

VHDL for an FPGA Engineer with Vivado Design Suite

Kumar Khandagle

VHDL for an FPGA Engineer with Vivado Design Suite

VHDL for an FPGA Engineer with Vivado Design Suite

(4.43 with 289 reviews)

2.2K

Building Processor with VHDL from Scratch

Kumar Khandagle

Building Processor with VHDL from Scratch

Building Processor with VHDL from Scratch

(4.57 with 14 reviews)

171

Building SDRAM Controller in Verilog from Scratch

Kumar Khandagle

Building SDRAM Controller in Verilog from Scratch

Building SDRAM Controller in Verilog from Scratch

(4.47 with 18 reviews)

215

PyUVM Series Part 1 : Python Fundamentals

Kumar Khandagle

PyUVM Series Part 1 : Python Fundamentals

PyUVM Series Part 1 : Python Fundamentals

(4.58 with 20 reviews)

153

PyUVM Series Part 2 : COCOTB fundamentals

Kumar Khandagle

PyUVM Series Part 2 : COCOTB fundamentals

PyUVM Series Part 2 : COCOTB fundamentals

(4.45 with 22 reviews)

199

Writing SystemVerilog Testbenches for Newbie

Kumar Khandagle

Writing SystemVerilog Testbenches for Newbie

Writing SystemVerilog Testbenches for Newbie

(4.48 with 530 reviews)

3.5K

students

Communication series P3 : AMBA AXI in Verilog

Kumar Khandagle

Communication series P3 : AMBA AXI in Verilog

Communication series P3 : AMBA AXI in Verilog

(4.54 with 67 reviews)

549

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

Kumar Khandagle

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

(4.54 with 2.1K reviews)

12.9K

Verification Series Part 6 : SystemVerilog Assertions Basics

Kumar Khandagle

Verification Series Part 6 : SystemVerilog Assertions Basics

Verification Series Part 6 : SystemVerilog Assertions Basics

(4.63 with 496 reviews)

1 2 3

45 minutes

content

Jun 2024

updated

FREE

students

7.7 hours

content

Jan 2025

updated

$17.99

students

20 hours

content

Jun 2023

updated

$14.99

students

3.7 hours

content

Jun 2023

updated

$14.99

students

4.8 hours

content

Apr 2025

updated

$17.99

students

4.1 hours

content

Jul 2024

updated

$17.99

students

4.0 hours

content

Jan 2025

updated

$17.99

8.4 hours

content

Jun 2022

updated

$14.99

students

9.3 hours

content

Dec 2024

updated

$17.99

students

17 hours

content

Jan 2025

updated

$17.99

3.7K

students

10 hours

content

Nov 2024

updated

$17.99