Building SDRAM Controller in Verilog from Scratch
(4.47 with 18 reviews)
215
students
4.8 hours
content
Apr 2025
updated
$17.99
Kumar Khandagle
Online Course Instructor
4.40 (12.2K reviews)
Statistics
79.8K
total students
204 hours
total content
May 2020
first content date
Apr 2025
last content date
Courses (24)
PyUVM Series Part 1 : Python Fundamentals
(4.58 with 20 reviews)
153
students
4.1 hours
content
Jul 2024
updated
$17.99
PyUVM Series Part 2 : COCOTB fundamentals
(4.45 with 22 reviews)
199
students
4.0 hours
content
Jan 2025
updated
$17.99
Writing SystemVerilog Testbenches for Newbie
(4.48 with 530 reviews)
3.5K
students
8.4 hours
content
Jun 2022
updated
$14.99
Communication series P3 : AMBA AXI in Verilog
(4.54 with 67 reviews)
549
students
9.3 hours
content
Dec 2024
updated
$17.99
Verilog for an FPGA Engineer with Xilinx Vivado Design Suite
(4.54 with 2.1K reviews)
12.9K
students
17 hours
content
Jan 2025
updated
$17.99
Verification Series Part 6 : SystemVerilog Assertions Basics
(4.63 with 496 reviews)
3.7K
students
10 hours
content
Nov 2024
updated
$17.99
PyUVM Series Part 4 : Python OOPS verification env projects
(2.25 with 2 reviews)
78
students
3.5 hours
content
Jan 2025
updated
$14.99
SystemVerilog Assertions (SVA) with Xilinx Vivado 2020.1
(4.60 with 51 reviews)
681
students
19 hours
content
Mar 2023
updated
$14.99
Learning UVM Testbench with Xilinx Vivado 2020
(4.54 with 79 reviews)
591
students
11 hours
content
Mar 2022
updated
$19.99
UVM Testbenches for Newbie
(4.57 with 574 reviews)
4.0K
students
4.7 hours
content
Nov 2022
updated
$14.99
Building a Processor with Verilog HDL from Scratch
(4.32 with 253 reviews)
1.8K
students
3.0 hours
content
Oct 2024
updated
$14.99
Communication Series P1 : UART, SPI and I2C in Verilog
(4.40 with 274 reviews)
2.8K
students
7.4 hours
content
Jun 2024
updated
$19.99
Embedded System Design with Xilinx Microblaze and SDK
(4.64 with 39 reviews)
295
students
7.5 hours
content
Jan 2022
updated
$14.99
Embedded System Design with Xilinx Zynq SoC and Vitis IDE
(4.25 with 144 reviews)
1.1K
students
11 hours
content
Sep 2022
updated
$19.99
Embedded System Design with Microblaze and Vitis IDE
(4.38 with 91 reviews)
610
students
8.1 hours
content
Jan 2022
updated
$14.99
Embedded System Design with Xilinx ZYNQ SoC and SDK
(4.36 with 107 reviews)
904
students
12 hours
content
Nov 2022
updated
$14.99
Building Custom AXI Interface Peripherals for ZYNQ Devices
(4.27 with 68 reviews)
658
students
7.1 hours
content
Nov 2021
updated
$19.99
Verification Series Part 5: UVM RAL Essentials
(4.55 with 455 reviews)
4.0K
students
7.2 hours
content
Jan 2025
updated
$17.99
Verification Series Part 4: UVM Projects
(4.49 with 564 reviews)
6.0K
students
8.7 hours
content
Mar 2025
updated
$19.99
Verification Series Part 3: UVM Essentials
(4.68 with 1.8K reviews)
9.8K
students
11 hours
content
Aug 2025
updated
$17.99
Verification Series Part 1: SystemVerilog Essentials
(4.48 with 3.6K reviews)
15.9K
students
14 hours
content
Feb 2025
updated
$19.99
Verilog Lint essentials for RTL Design Engineer
(4.52 with 26 reviews)
150
students
3.2 hours
content
Nov 2024
updated
$11.99
Verification Series Part 2: Hands-On SystemVerilog Projects
(4.52 with 847 reviews)
9.2K
students
8.0 hours
content
Jan 2025
updated
$14.99