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Kumar Khandagle

Kumar Khandagle

Online Course Instructor

4.42 (13.6K reviews)

Statistics

91.9K

total students

245 hours

total content

May 2020

first content date

Apr 2025

last content date

Courses (29)

📚 Other Courses (29)

Learning SystemVerilog Testbenches with Xilinx Vivado 2020

Kumar Khandagle

Learning SystemVerilog Testbenches with Xilinx Vivado 2020

Learning SystemVerilog Testbenches with Xilinx Vivado 2020

(4.55 with 93 reviews)

751

students

8.8 hours

content

Sep 2021

updated

$14.99

Resume Essentials for VLSI Internships and Entry-Level Jobs

Kumar Khandagle

Resume Essentials for VLSI Internships and Entry-Level Jobs

Related Topics

Resume & CV Writing Job Application & Interview P…VLSI Career Prep

Resume Essentials for VLSI Internships and Entry-Level Jobs

(4.42 with 72 reviews)

2.5K

students

45 minutes

content

Jun 2024

updated

FREE

Verification Series Part 7:SystemVerilog Functional Coverage

Kumar Khandagle

Verification Series Part 7:SystemVerilog Functional Coverage

Related Topics

SystemVerilog Hardware Verification Functional Coverage

Verification Series Part 7:SystemVerilog Functional Coverage

(4.48 with 346 reviews)

3.2K

students

7.7 hours

content

Jan 2025

updated

$17.99

VHDL for an FPGA Engineer with Vivado Design Suite

Kumar Khandagle

VHDL for an FPGA Engineer with Vivado Design Suite

VHDL for an FPGA Engineer with Vivado Design Suite

(4.43 with 289 reviews)

2.2K

students

20 hours

content

Jun 2023

updated

$14.99

Building Processor with VHDL from Scratch

Kumar Khandagle

Building Processor with VHDL from Scratch

Building Processor with VHDL from Scratch

(4.57 with 14 reviews)

171

students

3.7 hours

content

Jun 2023

updated

$14.99

Building SDRAM Controller in Verilog from Scratch

Kumar Khandagle

Building SDRAM Controller in Verilog from Scratch

Building SDRAM Controller in Verilog from Scratch

(4.47 with 18 reviews)

215

students

4.8 hours

content

Apr 2025

updated

$17.99

PyUVM Series Part 1 : Python Fundamentals

Kumar Khandagle

PyUVM Series Part 1 : Python Fundamentals

Related Topics

Python Programming Python Fundamentals UVM Verification Hardware Verification

PyUVM Series Part 1 : Python Fundamentals

(4.58 with 20 reviews)

153

students

4.1 hours

content

Jul 2024

updated

$17.99

PyUVM Series Part 2 : COCOTB fundamentals

Kumar Khandagle

PyUVM Series Part 2 : COCOTB fundamentals

Related Topics

Python Scripting & Automation UVM Verification Hardware Verification Cocotb Verification

PyUVM Series Part 2 : COCOTB fundamentals

(4.45 with 22 reviews)

199

students

4.0 hours

content

Jan 2025

updated

$17.99

Writing SystemVerilog Testbenches for Newbie

Kumar Khandagle

Writing SystemVerilog Testbenches for Newbie

Related Topics

SystemVerilog Testbench Development Hardware Verification

Writing SystemVerilog Testbenches for Newbie

(4.48 with 530 reviews)

3.5K

students

8.4 hours

content

Jun 2022

updated

$14.99

Communication series P3 : AMBA AXI in Verilog

Kumar Khandagle

Communication series P3 : AMBA AXI in Verilog

Related Topics

Verilog HDL AXI4 Bus Protocol Digital Circuit Design Hardware Interconnect

Communication series P3 : AMBA AXI in Verilog

(4.54 with 67 reviews)

549

students

9.3 hours

content

Dec 2024

updated

$17.99

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

Kumar Khandagle

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

Related Topics

Verilog HDL FPGA Design Xilinx Vivado

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

(4.54 with 2.1K reviews)

12.9K

students

17 hours

content

Jan 2025

updated

$17.99

Verification Series Part 6 : SystemVerilog Assertions Basics

Kumar Khandagle

Verification Series Part 6 : SystemVerilog Assertions Basics

Related Topics

SystemVerilog Assertions and Waits Hardware Verification Digital Circuit Design

Verification Series Part 6 : SystemVerilog Assertions Basics

(4.63 with 496 reviews)

3.7K

students

10 hours

content

Nov 2024

updated

$17.99

PyUVM Series Part 4 : Python OOPS verification env projects

Kumar Khandagle

PyUVM Series Part 4 : Python OOPS verification env projects

Related Topics

Python for Data Analysis Object-Oriented Python UVM Verification Verification Projects

PyUVM Series Part 4 : Python OOPS verification env projects

(2.25 with 2 reviews)

78

students

3.5 hours

content

Jan 2025

updated

$14.99

SystemVerilog Assertions (SVA) with Xilinx Vivado 2020.1

Kumar Khandagle

SystemVerilog Assertions (SVA) with Xilinx Vivado 2020.1

Related Topics

SystemVerilog Assertions and Waits Xilinx Vivado Hardware Verification

SystemVerilog Assertions (SVA) with Xilinx Vivado 2020.1

(4.60 with 51 reviews)

681

students

19 hours

content

Mar 2023

updated

$14.99

Learning UVM Testbench with Xilinx Vivado 2020

Kumar Khandagle

Learning UVM Testbench with Xilinx Vivado 2020

Related Topics

Validation & Verification Verilog HDL Xilinx Vivado

Learning UVM Testbench with Xilinx Vivado 2020

(4.54 with 79 reviews)

591

students

11 hours

content

Mar 2022

updated

$19.99

UVM Testbenches for Newbie

Kumar Khandagle

UVM Testbenches for Newbie

Related Topics

Validation & Verification Digital Logic & Hardware SystemVerilog EDA Tooling

UVM Testbenches for Newbie

(4.57 with 574 reviews)

4.0K

students

4.7 hours

content

Nov 2022

updated

$14.99

Building a Processor with Verilog HDL from Scratch

Kumar Khandagle

Building a Processor with Verilog HDL from Scratch

Related Topics

Verilog HDL Digital Circuit Design Processor Architecture Xilinx Vivado Computer Engineering

Building a Processor with Verilog HDL from Scratch

(4.32 with 253 reviews)

1.8K

students

3.0 hours

content

Oct 2024

updated

$14.99

Communication Series P1 : UART, SPI and I2C in Verilog

Kumar Khandagle

Communication Series P1 : UART, SPI and I2C in Verilog

Communication Series P1 : UART, SPI and I2C in Verilog

(4.40 with 274 reviews)

2.8K

students

7.4 hours

content

Jun 2024

updated

$19.99

Embedded System Design with Xilinx Microblaze and SDK

Kumar Khandagle

Embedded System Design with Xilinx Microblaze and SDK

Embedded System Design with Xilinx Microblaze and SDK

(4.64 with 39 reviews)

295

students

7.5 hours

content

Jan 2022

updated

$14.99

Embedded System Design with Xilinx Zynq SoC and Vitis IDE

Kumar Khandagle

Embedded System Design with Xilinx Zynq SoC and Vitis IDE

Embedded System Design with Xilinx Zynq SoC and Vitis IDE

(4.25 with 144 reviews)

1.1K

students

11 hours

content

Sep 2022

updated

$19.99

Embedded System Design with Microblaze and Vitis IDE

Kumar Khandagle

Embedded System Design with Microblaze and Vitis IDE

Embedded System Design with Microblaze and Vitis IDE

(4.38 with 91 reviews)

610

students

8.1 hours

content

Jan 2022

updated

$14.99

Embedded System Design with Xilinx ZYNQ SoC and SDK

Kumar Khandagle

Embedded System Design with Xilinx ZYNQ SoC and SDK

Embedded System Design with Xilinx ZYNQ SoC and SDK

(4.36 with 107 reviews)

904

students

12 hours

content

Nov 2022

updated

$14.99

Building Custom AXI Interface Peripherals for ZYNQ Devices

Kumar Khandagle

Building Custom AXI Interface Peripherals for ZYNQ Devices

Building Custom AXI Interface Peripherals for ZYNQ Devices

(4.27 with 68 reviews)

658

students

7.1 hours

content

Nov 2021

updated

$19.99

Verification Series Part 5: UVM RAL Essentials

Kumar Khandagle

Verification Series Part 5: UVM RAL Essentials

Related Topics

UVM Verification Hardware Verification UVM RAL Register Modeling

Verification Series Part 5: UVM RAL Essentials

(4.55 with 455 reviews)

4.0K

students

7.2 hours

content

Jan 2025

updated

$17.99

Verification Series Part 4: UVM Projects

Kumar Khandagle

Verification Series Part 4: UVM Projects

Verification Series Part 4: UVM Projects

(4.49 with 564 reviews)

6.0K

students

8.7 hours

content

Mar 2025

updated

$19.99

Showing 1–25 of 29 courses

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