VLSI/FPGA Design P3: Common Used Hardware Architectures
A Big Step Towards Complex IP Design
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206
students
10.5 hours
content
Mar 2025
last update
$19.99
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What you will learn
Behavior of SRAM and usage suggestions
Handshake interface and synchronous FIFO
Pipeline to maximal clock frequency
Arbiter
Cross clock domain (CDC) and asynchronous FIFO
Ping-Pong
Pipeline with control (feedback)
Pipeline with hazard and forward path
Slide window
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6370051
udemy ID
31/12/2024
course created date
30/07/2025
course indexed date
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