Unveiling UVM in SystemVerilog language: From Building UVM Agents to Functional Coverage and Debugging Techniques
InstructorCristian SlavEditorial course preview
This view highlights a concrete, legible example from the course presentation.
Presentation slide outlining course learning objectives, including building a verification environment and a final project scope.
The curriculum covers essential verification elements such as scoreboards, virtual sequencers, and synchronization logic for FIFO flags and IRQs.
Lessons pair video lectures with specific practice and info items, supporting a workflow of theory followed by implementation.
Effective use of the material may require a foundational understanding of UVM before starting the advanced environment construction.
The curriculum aligns with the target of module-level verification, though high prerequisites are noted.
