VSD - Functional Verification Using Embedded-UVM - Part 1

Introduction to Discrete Event Simulation Technology, Functional Verification, Getting acquainted with Simulation tools
4.04 (14 reviews)
Udemy
platform
English
language
Hardware
category
Kunal Ghosh
instructor
VSD - Functional Verification Using Embedded-UVM - Part 1
187
students
3 hours
content
Nov 2019
last update
$39.99
regular price

What you will learn

SoC design flow, role of Functional Verification

Logic Modeling, Introduction to Verilog

Concept of Hierarchy, Simulation-Time, and Concurrency in Hardware Modeling

Simulation Technology, Discrete Event Simulation

Verification Trends and Challenges

Concepts and Principles of Functional Verification

Testbench Architecture and Components

Lab – Tool Setup and Usage -- a simple DUT with traditional Verilog testbench will be provided with a Makefile to compile and simulate – Debug using waveforms

Course Gallery

VSD - Functional Verification Using Embedded-UVM - Part 1 – Screenshot 1
Screenshot 1 – VSD - Functional Verification Using Embedded-UVM - Part 1
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VSD - Functional Verification Using Embedded-UVM - Part 1 – Screenshot 3
Screenshot 3 – VSD - Functional Verification Using Embedded-UVM - Part 1
VSD - Functional Verification Using Embedded-UVM - Part 1 – Screenshot 4
Screenshot 4 – VSD - Functional Verification Using Embedded-UVM - Part 1

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udemy ID
02/11/2019
course created date
06/11/2019
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