Simple AXI bus Design using Verilog HDL
(3.50 with 11 reviews)
49
students
1.1 hours
content
Dec 2023
updated
$14.99
Surender Reddy T
Online Course Instructor
3.92 (460 reviews)
Statistics
1.9K
total students
14 hours
total content
Sep 2020
first content date
Dec 2023
last content date
Courses (4)
Complete Verilog HDL programming with Examples and Projects
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8.2 hours
content
Jun 2023
updated
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(3.90 with 49 reviews)
241
students
2.9 hours
content
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updated
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RISC processor with own Instruction Set Architecture (ISA)
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139
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updated
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