Simple AXI bus Design using Verilog HDL
(3.50 with 11 reviews)
49
students
1.1 hours
content
Dec 2023
updated
$14.99
Udemy instructor
Surender Reddy T
- Teaches
- IT & Software · Design
- Languages
- English
- Course index
- 40 live offers
- Students
- 1.9K
- Average rating
- 3.92
- First published
- Sep 2020
- Latest course
- Dec 2023
- Total content
- 14 hours
