Surender Reddy T

Developer
4.21 (434 reviews)
6
active courses
0
removed courses
Aug 2020
first content date
Aug 2024
last content date
Surender Reddy T
2087
total students
434
total reviews
4.21
average rating
20
total content length
Courses
Simple AXI bus Design using Verilog HDL

Simple AXI bus Design using Verilog HDL

43
students
1 hour
content
Dec 2023
updated
$13.99
Python Programming Hands-on

Python Programming Hands-on

159
students
4.5 hours
content
Aug 2024
updated
$13.99
RISC processor with own Instruction Set Architecture (ISA)

RISC processor with own Instruction Set Architecture (ISA)

125
students
1.5 hours
content
Oct 2021
updated
$13.99
Step by step hands-on design of UART using Verilog HDL

Step by step hands-on design of UART using Verilog HDL

220
students
3 hours
content
Jul 2022
updated
$39.99
Simple FIFO Design and Simulation using Verilog HDL

Simple FIFO Design and Simulation using Verilog HDL

226
students
1 hour
content
Jun 2021
updated
$13.99
Complete Verilog HDL programming with Examples and Projects

Complete Verilog HDL programming with Examples and Projects

1.3K
students
8 hours
content
Jun 2023
updated
$13.99

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