COMIDOC
Today
Daily Freebies
Coupons
Verified Coupons
Free
Free Courses
Search courses and topics
React
Advertise
Submit Course
Simple AXI bus Design using Verilog HDL - Udemy Coupon | Comidoc
AXI in easy understand
Udemy course
/
IT & Software
/
Hardware
Simple AXI bus Design using Verilog HDL
Instructor
Surender Reddy T
Duration
1h 4m
Students
49
Rating
3.5 (11)
Topics
Verilog HDL
AXI4 Bus Protocol
Digital Circuit Design
Hardware Interconnect
Sponsored
Price
$14.99
Coupon
None
No active coupon currently available
Access
60s wait
Sign in for faster access
Go to Course (Udemy website)
Buy Comidoc Premium
Instant redirect
Sponsored
More Verilog HDL courses
Verilog HDL: VLSI Hardware Design Comprehensive Masterclass
Shepherd Tutorials
4.4 (4,622)
12h 41m
Vivado Basics: Learn FPGA Design with a PCIe Project
Ofer Keren
3.8 (165)
8h
Verilog for an FPGA Engineer with Xilinx Vivado Design Suite
Kumar Khandagle
4.5 (2,051)
16h 37m
Verilog para FPGAs
Arturo Sacramento Lopez Gonzalez
4.3 (36)
5h 37m
System Design using Verilog
Dr. Yogesh Misra
4.5 (771)
30h 25m
FPGA Embedded Design, Part 1 - Verilog
Eduardo Corpeño
4.5 (1,135)
3h 43m
ASIC Design & Verification using Verilog HDL +Project Demo
VLSI Mentor
4.5 (146)
15h 58m
Mastering Digital VLSI, ASIC and Verilog Interview Questions
Life Skills
4.5 (415)
4h 33m
InstructorSurender Reddy TInstructorSurender Reddy T
