FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP
Udemy courseDesignDesign Tools
VSD - Mixed-signal RISC-V based SoC on FPGA
InstructorKunal GhoshDuration1h 16m
Students132
Rating3.9 (8)
Sponsored
Sponsored
FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP
InstructorKunal Ghosh