VSD - Mixed-signal RISC-V based SoC on FPGA

FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP

3.88 (8 reviews)

Udemy

platform

English

language

Design Tools

category

instructor

VSD - Mixed-signal RISC-V based SoC on FPGA

113

students

1.5 hours

content

Jul 2021

last update

$39.99

regular price

What you will learn

FPGA flow vs ASIC flow

Basic mixed-signal RISC-V based SoC RTL design and simulations

FPGA Synthesis, bit-stream generation and simulation

Course Gallery

VSD - Mixed-signal RISC-V based SoC on FPGA – Screenshot 1 — Screenshot 1 – VSD - Mixed-signal RISC-V based SoC on FPGA

VSD - Mixed-signal RISC-V based SoC on FPGA – Screenshot 2 — Screenshot 2 – VSD - Mixed-signal RISC-V based SoC on FPGA

VSD - Mixed-signal RISC-V based SoC on FPGA – Screenshot 3 — Screenshot 3 – VSD - Mixed-signal RISC-V based SoC on FPGA

VSD - Mixed-signal RISC-V based SoC on FPGA – Screenshot 4 — Screenshot 4 – VSD - Mixed-signal RISC-V based SoC on FPGA

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Related Topics

4185794

udemy ID

15/07/2021

course created date

18/07/2021

course indexed date

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