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VLSI Mentor

VLSI Mentor

Online Course Instructor

4.41 (665 reviews)

Statistics

15.7K

total students

87 hours

total content

Oct 2024

first content date

Dec 2024

last content date

Courses (4)

ASIC Verification using System Verilog (SV) + Project Demo

ASIC Verification using System Verilog (SV) + Project Demo

(4.34 with 55 reviews)

ASIC Design Verification using SV-UVM + Project Demo

ASIC Design Verification using SV-UVM + Project Demo

(4.40 with 41 reviews)

ASIC Design & Verification using Verilog HDL +Project Demo

ASIC Design & Verification using Verilog HDL +Project Demo

(4.47 with 146 reviews)

ASIC Synthesis-STA-Physical Design(PD):Cadence+Synopsys flow

ASIC Synthesis-STA-Physical Design(PD):Cadence+Synopsys flow

(4.43 with 423 reviews)

VLSI Mentor courses | Comidoc