Tolerance Stack-up Analysis of GD&T-From Beginners to Stars

Course participants will be trained to apply tolerance stack-up analysis techniques to a wide variety of assemblies per GD&T requirements of ASME Y14.5-2018, from the very simple to the more complex situations commonly faced in industry today. Both plus and minus and geometrically toleranced assemblies will be examined and stack-up analysis taught and practiced on each. Many different datum structures will be discussed and analyzed. The concepts taught in this course are: loop analysis (also known as circuit diagrams), inner and outer boundaries, minimum gap, maximum wall thickness, maximum interference, minimum and maximum overall dimensions, fixed and floating fastener assembly conditions, projected tolerance zones, the logic of stack-up analysis, statistical tolerancing , and much more.