VLSI/FPGA Design P4: STA && DC Synthesis

Static Timing Analysis and DC Synthesis
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Udemy
platform
English
language
Hardware
category
VLSI/FPGA Design P4: STA && DC Synthesis
80
students
8 hours
content
Apr 2025
last update
$19.99
regular price

What you will learn

Principle of STA

Basics of stander cell library

Characters of clock in STA

Setup/hold timing analysis for same clock

Common used timing constraints

Timing analysis for same clock domain (synchronous path)

Timing analysis for different clock domain (asynchronous path)

Synthesis example using Design Compiler (including whole TCL script)

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6460129
udemy ID
12/02/2025
course created date
27/03/2025
course indexed date
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course submited by
VLSI/FPGA Design P4: STA && DC Synthesis - | Comidoc