Vikas Sachdeva
Trainer at vlsideepdive
3.98 (28 reviews)
3
active courses
2
removed courses
May 2021
first content date
Feb 2022
last content date
67
total students
28
total reviews
3.98
average rating
18
total content length
Courses
VLSI Design Flow
16
students
2.5 hours
content
Feb 2022
updated
$39.99
Clock Domain Crossing Design & Verification (CDC)
26
students
2 hours
content
Aug 2021
updated
$199.99
STA and Timing Constraints
23
students
2.5 hours
content
Aug 2021
updated
$199.99
Related Topics
Verilog HDL Programming
Digital Circuit
Static Timing Analysis
VLSI
Vikas Sachdeva courses | Comidoc
