Subir Maity
Researcher and Academician
4.36 (227 reviews)
4
active courses
0
removed courses
Sep 2022
first content date
Jun 2025
last content date
2278
total students
227
total reviews
4.36
average rating
15
total content length
Courses
Designing RISC-V CPU in Verilog and its FPGA Implementation
9
students
6 hours
content
Jun 2025
updated
$19.99
