Verilog HDL Fundamentals for Digital Design and Verification

Build a strong Verilog language foundation by implementing combinational / sequential digital circuits and testbenches

4.45 (1254 reviews)

Udemy

platform

English

language

Hardware

category

Ovidiu Plugariu

instructor

Verilog HDL Fundamentals for Digital Design and Verification

6 916

students

5.5 hours

content

Jun 2024

last update

$84.99

regular price

What you will learn

Master the basics of Verilog language for designing synthesizable digital circuits for ASIC / FPGA

Differentiate between Verilog structural / dataflow / behavioral design styles and how / when to use them in Digital Design and Verification

Implement combinational and sequential digital circuits using Verilog HDL starting from schematics or functional specifications

Create and simulate a Verilog testbench for a digital circuit starting from its functional specifications

Examine the behavior of a digital circuit receiving stimulus in a testbench, using an industry-level simulator (free for academic purposes)

Explicit visual explanations for the 80+ downloadable code examples, circuits, and testbenches offering you increased retention and accelerated learning

Screenshots

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Related Topics

Verilog HDL Programming

4261466

udemy ID

24/08/2021

course created date

27/09/2021

course indexed date

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