High-Level Synthesis for FPGA, Part 2 - Sequential Circuits

Logic Design with Vitis-HLS
4.65 (161 reviews)
Udemy
platform
English
language
Hardware
category
Mohammad Hosseinbady
instructor
High-Level Synthesis for FPGA, Part 2 - Sequential Circuits
2 165
students
9.5 hours
content
Mar 2023
last update
$74.99
regular price

What you will learn

Designing sequential logic circuits with C/C++ language using the HLS approach

Understanding the basic concepts of High-Level Synthesis (HLS)

Using HLS concepts for designing sequential logic circuits

HLS design flow for FPGAs

Working with Xilinx Vitis-HLS and Vivado design suite Toolsets

How to generate RTL hardware IPs using Vitis-HLS

Writing C-testbench in HLS

Implementing three exciting projects with HLS

Screenshots

High-Level Synthesis for FPGA, Part 2 - Sequential Circuits - Screenshot_01High-Level Synthesis for FPGA, Part 2 - Sequential Circuits - Screenshot_02High-Level Synthesis for FPGA, Part 2 - Sequential Circuits - Screenshot_03High-Level Synthesis for FPGA, Part 2 - Sequential Circuits - Screenshot_04
Related Topics
3639976
udemy ID
17/11/2020
course created date
30/03/2021
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