VERILOG / VHDL guided project tutorial UART design on FPGA

Design of UART on FPGA using VHDL / verilog programming (Guided project)
4.62 (21 reviews)
Udemy
platform
English
language
Hardware
category
Ezeuko Emmanuel
instructor
VERILOG / VHDL guided project tutorial UART design on FPGA
77
students
3.5 hours
content
Oct 2023
last update
$13.99
regular price

What you will learn

the student will learn how to design a half-duplex and also a full duplex transceiver.

the student will learn about baud rates, how to design one and the different lists of standard baud rates

the student will learn how to design a UART serial communication protocol and implement it on an FPGA Board

design UART transmitter AND receiver on FPGA with vhdl code, and simulate on logism

the student will learn how to convert serial bits to parallel bits and vice versa, and also implement in VHDL

the student will also learn some commonly used VHDL structural blocks like shift registers, parallelizer, serializer,

design UART transceiver on FPGA with vhdl code, and simulate on logism

Course Gallery

VERILOG / VHDL guided project tutorial UART design on FPGA – Screenshot 1
Screenshot 1 – VERILOG / VHDL guided project tutorial UART design on FPGA
VERILOG / VHDL guided project tutorial UART design on FPGA – Screenshot 2
Screenshot 2 – VERILOG / VHDL guided project tutorial UART design on FPGA
VERILOG / VHDL guided project tutorial UART design on FPGA – Screenshot 3
Screenshot 3 – VERILOG / VHDL guided project tutorial UART design on FPGA
VERILOG / VHDL guided project tutorial UART design on FPGA – Screenshot 4
Screenshot 4 – VERILOG / VHDL guided project tutorial UART design on FPGA

Loading charts...

Related Topics

4927640
udemy ID
13/10/2022
course created date
25/10/2022
course indexed date
Bot
course submited by